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For most things these 2 chips are the same, however if you look at them you notice one difference. The Z can only address 62k of memory while the Z can do an entire 64k. Further research shows that the Z must be run in Test Mode to function. Thus addresses start at 2K leaving only 62K available. The Z added a power down function though I have not actually seen one. Its likely it was announce, but never made it to production like the Z ZiLOG also released the Z in It was not compatible with nor based on the Z Being it was released the same time as the Intel and Motorola MC as well as the National 32K and a few other competing designs, it did not do very well.

The Z was made in two main versions: The higher end Z which, by use of segmentation, could address up to 8Mb of memory, and the Z which could only address 64k. Memory segmentation works by essentially having 2 address buses. First a 7-bit segment is selected so segments possible then the word is selected with a 16 bit address. This required an extra 7 pins and thus the Z came in a 48 pin DIP.

Jump to program location addressed by register pair ! This offset is added to the register address and the resulting address points to the location whose value is used by the instruction. This address is followed by the index, a working-register designator enclosed in parentheses.

Since the specified register address and working register contents are both 8-bit values, the indexed-address mode can be used for base addressing. The base address is loaded into the working register and the offset register address then completes the address field. The address may be specified as an expression which evaluates to a number or a program label. IJump to location hex if the carry flag is set! The operand, in this case, represents an offset that is added to the contents of the program counter to form the destination address the program address where control is to be transferred.

The original contents of the program counter is taken to be the address of the instruction byte following the JR or DJNZ instruction, while the offset value is an 8-bit signed value in the range to Add value of constant K to program counter and jump to new location if overflow has occurred! In the second method , the assembler calculates the offset. The programmer simply specifies an expression which evaluates to a number or a program label as in direct addressing.

Refer to Section 5. The operand value used by the instruction in this :ase is the value supplied in the operand field itself. The Z8 is optimized for this function, providing several short immediate data instructions to reduce the byte count of programs. Immediate data is preceded by the special character and may be a constant including character constants and symbols representing constants or an expression as described in section 2.

Remember, if a variable name is prefixed by , the value used is the address represented by the variable, not the contents of the address. Immediate data values must be in the range to that is, expressible in 8 bits , or an error message will be generated. Two special operators are provided to ease the manipulation of bit addresses: the HI operator gives the high-order byte, and LO gives the low-order byte of a bit expression.

Since HI and LO can only be used where the immediate addressing mode is applicable, the character must precede them. The assembler determines the appropriate binary instruction code so that the specified working-register address can be formed at run time using the current value of the register pointer.


The upper four bits of the memory address are taken from the register pointer; the lower four bits are taken from the instruction code, and together they specify the designated working register. When programming in binary code, an additional possibility exists. When a full 8-bit register designator is required by the instruction format register or register-pair address modes , a working register or working-register pair can be specified without knowing the current value of the register pointer.

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If the upper nibble of the register field is coded as a hexadecimal E, the lower nibble is interpreted as a working-register EO-EF hex are not implemented register addresses. The final register address is formed at run time by replacing E with the register pointer value. This mechanism is handled automatically by the assembler whenever a working register designator is used.

The working-register mechanism allows sections of code using different register-pointer values to share a common procedure and pass parameters to it via the working registers. In addition to symbols already listed above, the following are also used in these summaries. The form addr n is used to refer to bit n of a given location.

For example, dst 7 refers to bit 7 of the destination byte. The result is stored in the destination location. The AND operation results in a one bit being stored whenever the bits matched in the two operands are both ones. The program counter value used is the address of the first instruction byte following the CALL instruction. The specified destination address is then loaded into the PC and points to the first instruction of a procedure.

At the end of the procedure a RETurn instruction can be used to return to the original program flow. RET pops the top of the stack back into the PC. No flags affected. The program counter now points to the address of the first statement in the procedure to be executed. The contents of the destination byte are unaffected by the comparison. The sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic. If the contents of the register are not zero after decrementing, the relative address is added to the program counter PC and control passes to the statement whose address is now in the PC.

When the working-register counter reaches zero, control falls through to the statement following DJNZ. The result of such an oopraHnn i q undefined. In this example, 12 bytes are moved from one buffer area in the register file to another. The steps involved are: 1. Load 12 into the counter working register 6 2. Set up the loop to perform the moves 3. New location! This allows any potentially enabled interrupts to become enabled.

It restores the flag register control register and the program counter.


It also reenables any interrupts that are potentially enabled. All flags are restored to original settings before interrupt occurred. See section 3. The unconditional jump simply replaces the contents of the program counter with the contents of the specified register pair. Control then passes to the statement addressed by the program counter. Had the carry flag not been set, control would have fallen through to the statement following the JP.